1. Field of the Invention
The present invention relates to comparators, and in particular, to chopper type comparators.
2. Prior Art
Chopper type comparators are conventionally known, for example, the circuit having a design such as that shown in FIG. 1. In the illustrated circuit, analog input voltage terminals 1 and 2 are provided, to each of which respective analog input voltage V.sub.1 and V.sub.2 are supplied. The analog input voltage terminal 1 connects to an analog switch 3 which is in turn made up of an N channel MOS (metal oxide semiconductor) transistor 3.sub.1 and a P channel MOS transistor 3.sub.2. The analog switch 3 is constructed such that when a gate a is low and a gate b is high in terms of the voltage levels applied thereto, current is conducted therethrough, whereas when the gate a is high and the gate b is low, current is not conducted.
A control input voltage terminal 4 is provided, to which a control input voltage V.sub.c is supplied. The control input voltage V.sub.c is inverted in an inverter 5. An analog switch 6 connects to the output terminal of the analog switch 3. The analog switch 6 is made up of an N channel MOS transistor 6.sub.1 and a P channel MOS transistor 6.sub.2, and is identical in structure and operation to the analog switch 3 described above.
One terminal of a capacitor 7 connects to the output terminals of the analog switch 3 and the analog switch 6 at a terminal T.sub.1. The other terminal of the capacitor 7 connects to the input terminal of an inverter 8 and with one terminal of an analog switch 9 at a terminal T.sub.2. As the analog switches 3 and 6, the analog switch 9 is made up of an N channel MOS transistor 9.sub.1 and a P channel MOS transistor 9.sub.2. Each of elements 7 through 9 described above together form a comparator unit 10. In certain implementations of the kind of the chopper type comparator shown in FIG. 1, the multiple comparator units 10 are incorporated and connected together thereby forming a multiple-stage comparator. An output terminal 11 for the comparator unit 10 and for the chopper type comparator as a whole is provided, which is connected to the output terminal of the inverter 8 as well as with the analog switch 9.
With the chopper type comparator as described above, the gate a of the analog switch 3 and that of the analog switch 9 and and the gate b of the analog switch 6 are all directly connected to the control input voltage terminal 4, whereas the gate b of the analog switch 3 and that of the analog switch 9 and the gate a of the analog switch 6 are all directly connected to the output of the inverter 5 wherein the control input voltage V.sub.c applied at the control input voltage terminal 4 is inverted. As a result, when the control input voltage V.sub.c applied at the control input voltage terminal 4 is low in terms of the voltage level applied thereto, the gate a of the analog switch 3 and that of the analog switch 9 and the gate b of the analog switch 6 are all in a low state and the gate b of the analog switch 3 and that of the analog switch 9 and the gate a of the analog switch 6 are all in a high state. Conversely, when the control input voltage V.sub.c applied at the control input voltage terminal 4 is high, the gate a of the analog switch 3 and that of the analog switch 9 and the gate b of the analog switch 6 are all in a high state and the gate b of the analog switch 3 and that of the analog switch 9 and the gate a of the analog switch 6 are all in a low state.
Because of the features described in the preceding paragraph, the analog switches 3 and 9 are always in the same state and the analog switch 6 is always in the opposite state compared with the analog switches 3 and 9. In other words, when the control input voltage V.sub.c applied at the control input voltage terminal 4 is low, the analog switch 6 is nonconductive and the analog switches 3 and 9 are conductive, whereas when the control input voltage V.sub.c applied at the control input voltage terminal 4 is high, the analog switch 6 is conductive and the analog switches 3 and 9 are nonconductive.
Accordingly, when the analog input voltages V.sub.1 and V.sub.2 are simultaneously applied to the analog input voltage terminals 1 and 2, respectively, and the control input voltage V.sub.c applied at the control input voltage terminal 4 is low, the analog input voltage V.sub.1 is output from the analog switch 3 and applied to the capacitor 7 at the terminal T.sub.1. The opposite terminal T.sub.2 of the capacitor 7 is connected directly with one terminal of the analog switch 9, and with the other terminal of the analog switch 9 after being electronically inverted in the inverter 8. Because the analog switch 9 is conductive when the control input voltage Vc is low, a short circuit is effectively formed between the terminal T.sub.2 and the terminal T.sub.3.
The above mentioned inverter 8 consists of a CMOS (complementary metal oxide) circuit constructed in turn from complementary FETs (complementary field effect transistors). When the properties of the FETs incorporated in the CMOS circuit making up the inverter 8 are highly uniform, and when the control input voltage V.sub.c applied at the control input voltage terminal 4 is low, the voltage at the terminals T.sub.2 and T.sub.3 is one half of a supplied power source voltage V.sub.DD which is supplied to the inverter 8, in other words, the voltage between the terminals T.sub.2 and T.sub.3 is equal to (1/2).multidot.V.sub.DD. Under these conditions, the potential difference across the capacitor 7 is equal to (V1- (1/2).multidot.V.sub.DD. In response to this potential difference across the capacitor 7, that is, in response to this potential difference between the terminals T.sub.1 and T.sub.2, an electrical charge is accumulated in the capacitor 7.
When the control input voltage V.sub.c applied at the control input voltage terminal 4 is then caused to jump to high, the gate a of the analog switch 3 and that of the analog switch 9 and the gate b of the analog switch 6 are then all in a high state and the gate b of the analog switch 3 and that of the analog switch 9 and the gate a of the analog switch 6 are all in a low state. Accordingly, the analog switch 6 becomes conductive and the analog switches 3 and 9 become nonconductive, for which reason the analog input voltage V.sub.2 output from the analog switch 6 is applied to the capacitor 7 at the terminal T.sub.1. Because the analog switch 9 is nonconductive and thus acts as an open circuit when the control input voltage V.sub.c is high, the opposite terminal T.sub.2 of the capacitor 7 at the terminal T.sub.2 is effectively connected only with the input terminal of the inverter 8, and the output terminal of the inverter 8 is effectively connected only with the output terminal 11.
Before the control input voltage V.sub.c applied at control input voltage terminal 4 was caused to jump to high, the potential difference across the capacitor 7 was equal to V.sub.1 -(1/2).multidot.V.sub.DD. thus the charge accumulated in the capacitor 7 was in response to a potential difference of (V.sub.1 -(1/2).multidot.V.sub.DD) thereacross. When the control input voltage V.sub.c jumps to high, and the voltage at the terminal T.sub.1 therefore changes to V.sub.2, the voltage at terminals T.sub.2 then becomes to (V.sub.2 -V.sub.1 +(1/2).multidot.V.sub.DD).
Referring to FIG. 2 which shows a graph of the characteristic curve of the output voltage V.sub.out of the inverter 8 as a function of the input voltage V.sub.in thereof, it can be seen that the slope is greatest when the analog switch 9 is in the conducting state, that is, when the inverter 8 is connected as a short circuit. For this reason, when the input voltage V.sub.in is in the vicinity of (1/2).multidot.V.sub.DD, small changes in the magnitude thereof result in large changes in the output voltage V.sub.out. In consideration of these characteristics, it can be seen that when V.sub.2 &gt;V.sub.1, the output voltage level at the terminal T.sub.3 of the inverter 8 will be low, whereas when V.sub.1 &gt;V.sub.2, that of the terminal T.sub.3 will be high. Based on these characteristics, comparison of the magnitude of the voltage V.sub.1 relative to the magnitude of the voltage V.sub.2 can be carried out. By connecting a plural of the comparator units 10 such as multiple stages, the overall gain of the chopper type comparator can be increased.
With this type of conventional chopper type comparator, when the analog switch 9 is turned on or off, in particular, when analog switch 9 transits from a conducting state to a nonconducting state, spike noise is mixed with the analog input voltage through the gate electrostatic capacitance, and is thereby made to introduce the spike noise. Thus, the potential at terminal T.sub.2 deviates from (1/2).multidot.V.sub.DD by a voltage variation .DELTA.V.sub.A.
Furthermore, with this kind of chopper type comparator, when the potential at the terminal T.sub.3 at the output lead of the inverter 8 changes from (1/2).multidot.V.sub.DD to high, or from (1/2).multidot.V.sub.DD to low, via junction capacitance in the analog switch 9, the change in potential at the terminal T.sub.3 leads to a change of potential at the terminal T.sub.2 by the voltage variation .DELTA.V.sub.A.
When the above described voltage variation .DELTA.V.sub.A is greater than V.sub.2 -V.sub.1, it becomes impossible to compare the potential of T.sub.3 and T.sub.2. For this reason, it is important to minimize the magnitude of any voltage variation .DELTA.V.sub.A so as to provide sufficiently accurate comparator operation. By selecting the capacitor 7 such that the capacitance thereof is relatively large relative to the charge of the gate electrostatic capacitance and the junction capacitance of the analog switch 9, the magnitude of the voltage variation .DELTA.V.sub.A can be diminished. Herein, the junction capacitance of the analog switch 9 is defined as four parts; that is, a PN junction capacitance which exists between a source and a substrate in P channel; a PN junction capacitance which exists between a drain and a substrate in P channel; a PN junction capacitance which exists between a source and a substrate in N channel and a PN junction capacitance which exists between a drain and a substrate in an N channel.
Thus, by increasing the capacitance of the capacitor 7 in the type of the conventional chopper type comparator shown in FIG. 1, the accuracy thereof was improved. Increasing the capacitance of the capacitor 7, however, has the effect of prolonging the time required for charging and discharging the capacitor 7, thereby leading to a marked loss in ability to carry out high speed comparisons which is decidedly undesirable.